A switched-current sample-and-hold circuit

Author

Hu, Xiaoyun ; Martin, Kenneth W.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

32

Issue

6

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

898

Lastpage

904

Abstract

A switched-current sample-and-hold circuit is reported. The circuit was fabricated in a 0.8-μm BiCMOS process. Measurements indicate a sampling frequency of 57 MHz with 60 dB signal-to-noise-plus-distortion-ratio and suggest that operation at sampling frequencies beyond 80 MHz is feasible. Comparisons of this circuit with other switched-current sample-and-hold circuits are given to highlight the strengths and weaknesses of the circuit. The feasibility of the sample-and-hold circuit as an under-sampler intended for the Canadian CT2Plus personal communication system is also presented

Keywords

BiCMOS analogue integrated circuits; SPICE; circuit analysis computing; integrated circuit design; integrated circuit measurement; integrated circuit noise; personal communication networks; radio receivers; sample and hold circuits; switched current circuits; 0.8 mum; 57 MHz; BiCMOS process; Canadian CT2Plus personal communication system; HSPICE simulation; current-mode architecture; design issues; receiver; sampling frequency; signal-to-noise-plus-distortion-ratio; switched-current sample-and-hold circuit; under-sampler; Bandwidth; Communication switching; Energy consumption; Frequency shift keying; Image sampling; Radio frequency; Receivers; Signal sampling; Switching circuits; Telephony;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.585292

Filename

585292