A high-speed median circuit

Author

Opris, Ion E. ; Kovacs, Gregory T A

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

32

Issue

6

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

905

Lastpage

908

Abstract

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-μm CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm ², and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor

Keywords

CMOS analogue integrated circuits; active filters; analogue processing circuits; circuit optimisation; integrated circuit design; median filters; nonlinear network synthesis; 2 mum; 200 ns; 30 pF; 5 V; 7 mW; Orbit 2-μm CMOS process; active area; cascode error amplifiers; design optimization; error minimization; external 30 pF capacitor driving; fast transient recovery; high-speed analog median circuit; low crossover distortion; median filtering; power dissipation; transition corners; two-stage architecture; Active filters; CMOS process; Circuits; Design optimization; Differential amplifiers; Filtering; Process design; Prototypes; Transient response; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.585296

Filename

585296