A fast parallel squarer based on divide-and-conquer

Author

Yoo, Jae-tack ; Smith, Kent F. ; Gopalakrishnan, Ganesh

Author_Institution

Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

Volume

32

Issue

6

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

909

Lastpage

912

Abstract

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation

Keywords

CMOS logic circuits; VLSI; digital arithmetic; 2 micron; 8 bit; CMOS fabrication technology; divide/conquer recursion; fast parallel squarer; image compression; optimized n-bit primitive squarers; CMOS technology; Circuit testing; Digital arithmetic; Energy consumption; Equations; Fabrication; HDTV; High speed integrated circuits; Image coding; Integrated circuit technology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.585298

Filename

585298