A CMOS mismatch model and scaling effects

Author

Wong, Shyh-Chyi ; Pan, Kuo-Hua ; Ma, Dye-Jyun

Author_Institution

Dept. of Electron. Eng., Feng Chia Univ., Taichung, Taiwan

Volume

18

Issue

6

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

261

Lastpage

263

Abstract

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a /spl radic/n-law model is developed for modeling gate-finger dependence of mismatch.

Keywords

CMOS analogue integrated circuits; MOSFET; SPICE; circuit analysis computing; integrated circuit modelling; semiconductor device models; /spl radic/n-law model; CMOS mismatch model; HSPICE simulation; SPICE mismatch simulation; analog circuits; body factor mismatch; circuit simulation; current factor mismatch; gate-finger dependence; global variations; local edge roughness; mismatch distributions; offset estimation; scaling effects; short-channel MOS devices; single-pair mismatch model; source resistance mismatch; statistical mismatch data; threshold voltage mismatch; Analog circuits; Circuit simulation; Data mining; Immune system; MOS devices; Predictive models; SPICE; Semiconductor device modeling; Semiconductor process modeling; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.585349

Filename

585349