• DocumentCode
    1547433
  • Title

    Hardware implementation of RAM-based neural networks for tomographic data processing

  • Author

    Williams, P. ; York, T.

  • Author_Institution
    Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci. & Technol., UK
  • Volume
    146
  • Issue
    2
  • fYear
    1999
  • fDate
    3/1/1999 12:00:00 AM
  • Firstpage
    114
  • Lastpage
    118
  • Abstract
    The hardware discussed in the paper employs field programmable logic devices to interface with memory components and unlike previous implementations, utilises dynamic RAM without compromising performance. The network offers the opportunity to estimate process parameters without recourse to image reconstruction. Tests reveal speedups of 17, 22 and 6 for image reconstruction, void fraction estimation and flow regime classification, respectively, from electrical capacitance tomography data
  • Keywords
    DRAM chips; computerised tomography; image reconstruction; neural nets; RAM-based neural networks; dynamic RAM; field programmable logic devices; flow regime classification; image reconstruction; performance; process parameters; tomographic data processing; void fraction estimation;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:19990123
  • Filename
    784742
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1547433