Minimising power dissipation in partial scan sequential circuits

Recently a new test application strategy for minimising of power dissipation during test applications in full scan sequential circuits was proposed. This paper investigates its applicability to partial scan sequential circuits. It is shown that, when compared to full scan sequential circuits, partial scan not only reduces the test area overhead and test application time, but also reduces the power dissipation during test applications and the computational time required for low power testable design space exploration