A CMOS codec chip for a cost effective Group 4 Fax system

Author

Seo, Seok Ho ; Park, Hong June ; Hong, Ki Sang ; Kim, Jae Ho ; Kim, Yoon Soo ; Park, Ki Wung

Author_Institution

Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea

Volume

43

Issue

2

fYear

1997

fDate

5/1/1997 12:00:00 AM

Firstpage

81

Lastpage

91

Abstract

A CMOS codes chip for image coding and decoding of a Group 4 Fax system was designed, fabricated and tested. The fabricated codec chip operates in a parallel pipelined scheme to enhance the throughput and shares a single SRAM chip as a buffer memory with other image processing modules to reduce the system cost. The architecture and the size of coding and decoding LUTs (look up tables) were optimized for the internal 16 bit DSP core used in the codec chip. A new algorithm for changing pel (picture element) detection without duplicate data readings from the external buffer memory was adopted to enhance the system speed

Keywords

CMOS digital integrated circuits; SRAM chips; buffer storage; codecs; decoding; digital signal processing chips; facsimile; image coding; parallel architectures; pipeline processing; table lookup; 16 bit; CMOS codec chip; DSP core; Group 4 Fax system; SRAM chip; algorithm; buffer memory; changing picture element detection; image coding; image decoding; image processing modules; look up tables; parallel pipelined scheme; system cost reduction; system speed; throughput; Codecs; Costs; Decoding; Digital signal processing chips; Image coding; Image processing; SRAM chips; System testing; Table lookup; Throughput;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.585525

Filename

585525