Title :
Fast adders using enhanced multiple-output domino logic
Author :
Wang, Zhongde ; Jullien, Graham A. ; Miller, William C. ; Wang, Jinghong ; Bizzan, Sami S.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
fDate :
2/1/1997 12:00:00 AM
Abstract :
Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-μm CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path
Keywords :
CMOS logic circuits; adders; carry logic; digital arithmetic; 1.2 micron; 2.7 ns; 32 bit; CLA adder; CMOS technology; carry lookahead adder; enhanced multiple-output domino logic; fast adders; sparse carry chain architecture; Adders; CMOS logic circuits; CMOS technology; Councils; Delay; Fabrication; Hardware; Microelectronics; Telecommunications; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
