A high-speed, low-power bipolar digital circuit for Gb/s LSI´s: current mirror control logic

Author

Kishine, Keiji ; Kobayashi, Yoshiji ; Ichino, Haruhiko

Author_Institution

NTT Syst. Electron. Labs., Kanagawa, Japan

Volume

32

Issue

2

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

215

Lastpage

221

Abstract

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)

Keywords

bipolar logic circuits; emitter-coupled logic; flip-flops; large scale integration; -2 V; 1.8 mW; 3.1 Gbit/s; 4.3 GHz; ECL series gate circuits; Gb/s LSI; bipolar IC; current mirror circuits; current mirror control logic; differential pairs; emitter-coupled-logic; high-speed operation; low-power bipolar digital circuit; Clocks; Current supplies; Digital circuits; Energy consumption; Latches; Logic circuits; Mirrors; Power dissipation; Power supplies; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.551913

Filename

551913