Fully Understanding the Mechanism of Misalignment-Induced Narrow-Transistor Failure and Carefully Evaluating the Misalignment-Tolerant SRAM-Cell Layout

We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, we have performed an intentionally misaligned experiment using a test structure with each SRAM block featuring a neighbor alignment-inspection mark. Moreover, utilizing the result of the experiment, we have created a manufacturing-friendly methodology of misalignment-limit determination.