A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection

Author

Shih, Tanchu ; Der, Lawrence ; Lewis, Stephen H. ; Hurst, Paul J.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

32

Issue

2

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

250

Lastpage

253

Abstract

A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-μm CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-μm CMOS process, the comparator occupies 0.25 mm² and dissipates 1.05 mW

Keywords

CMOS integrated circuits; analogue processing circuits; analogue-digital conversion; comparators (circuits); switched capacitor networks; 1.05 mW; 2 micron; 25 MHz; 3 bit; 3.3 V; 7 MHz; CMOS process; SC circuit; analog/digital converter; common-mode rejection; flash ADC; fully differential comparator; switched-capacitor differencing circuit; Analog-digital conversion; CMOS process; CMOS technology; Capacitors; Integrated circuit noise; Laboratories; Preamplifiers; Solid state circuits; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.551918

Filename

551918