DocumentCode :
1548351
Title :
Single chip video processor for digital HDTV
Author :
Yamauchi, Hideki ; Okada, Shigeyuki ; Taketa, Kazuhiko ; Mihara, Yoshikazu ; Harada, Yasoo
Author_Institution :
Sanyo Electr. Co. Ltd., Gifu, Japan
Volume :
47
Issue :
3
fYear :
2001
fDate :
8/1/2001 12:00:00 AM
Firstpage :
394
Lastpage :
404
Abstract :
We have developed a single chip video processor integrated TS decoder, MPEG-2 MP@HL decoder and OSD controller for BS digital broadcasting. The video processor is available for all the formats of digital broadcasting and displays output on the “Hi-Vision” (high-definition) CRT in SDTV as well as HDTV. Also, 4-channel decoding/display and multi-angle broadcasting of digital TV is obtained. It has excellent functions such as seamless display, audio/video (AV) synchronization, error concealment, etc. Adoption of a cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequency reduction, circuit miniaturization, design simplification, high-performance service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip video processor is manufactured of 0.25-μm four-layer metal CMOS process and the chip size is 10.2 mm×10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz
Keywords :
CMOS digital integrated circuits; decoding; digital signal processing chips; digital television; high definition television; parallel architectures; video signal processing; 0.25 micron; 121.5 MHz; 2.5 V; 4-channel decoding/display; 4.5 W; AV synchronization; BS digital broadcasting; CMOS process; Hi-Vision; MPEG-2 MP@HL decoder; OSD controller; SDTV; TS decoder; TV broadcasting regulation change; audio/video synchronization; chip size; circuit miniaturization; cooperative processing architecture; design simplification; digital HDTV; equipment specification change; error concealment; high-performance service; multi-angle broadcasting; operating frequency; operating frequency reduction; parallel bus architecture; pipeline architecture; power consumption; seamless display; single chip video processor; supply voltage; Auditory displays; Computer architecture; Decoding; Digital TV; Digital audio broadcasting; Digital control; Digital video broadcasting; Frequency; HDTV; TV broadcasting;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.964126
Filename :
964126
Link To Document :
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