Title :
Comments on “Leading-zero anticipatory logic for high-speed floating point addition” [with reply]
Author :
Oklobdzija, V. ; Suzuki, Hajime ; Makino, Hiroaki ; Nakase, Yasunobu ; Mashiko, K. ; Sumi, Takuya
Author_Institution :
Integration, Berkeley, CA
fDate :
2/1/1997 12:00:00 AM
Abstract :
For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. However, I found the LZ counter circuit shown in the paper similar to the LZ counter circuit that I have published previously in the period from 1992-94
Keywords :
floating point arithmetic; LZ counter circuit; high-speed floating point addition; leading-zero anticipatory logic; Algorithm design and analysis; Application specific integrated circuits; Asia; Circuit synthesis; Counting circuits; Delay; Detectors; Logic; Signal design; Tree data structures;
Journal_Title :
Solid-State Circuits, IEEE Journal of
