DocumentCode
1548537
Title
An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder
Author
Takizawa, Tetsuro ; Hirasawa, Masao
Author_Institution
Multimedia Res. Labs., NEC Corp., Japan
Volume
47
Issue
3
fYear
2001
fDate
8/1/2001 12:00:00 AM
Firstpage
660
Lastpage
665
Abstract
This paper presents an efficient memory arbitration algorithm for a system on a chip. We have implemented the algorithm into a single chip MPEG2 AV decoder. According to simulations, the memory access efficiency of the arbiter based on the new algorithm is around 95% with a 32-bit 133 MHz SDRAM, while those of conventional arbiters are less than 80%
Keywords
CMOS memory circuits; DRAM chips; asynchronous circuits; audio coding; data compression; decoding; digital signal processing chips; memory architecture; video coding; 133 MHz; 32 bit; CMOS process; SDRAM; arbiter; digital TV sets; efficient memory arbitration algorithm; memory access efficiency; simulations; single chip MPEG2 AV decoder; system on a chip; unified memory architecture; Costs; Decoding; Digital TV; Large scale integration; National electric code; SDRAM; Streaming media; System buses; US Department of Transportation; Video sharing;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/30.964160
Filename
964160
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