Novel PLL-based frequency synthesiser without using the frequency divider

A technique of implementing a PLL-based frequency synthesiser (FS) without using the frequency divider sub-circuit has been discussed. To generate the loop oscillator control signal, proportional to the phase mismatch between the reference signal and the synthesised signal (where the frequency of the latter is a multiple of that of the former), the proposed structure uses a phase detector used in data clock recovery circuits with some modification. The operating conditions of the proposed system have been analytically examined and the results of a prototype hardware experiment carried out around 500 kHz are given. The study confirms the possibility of designing a dividerless indirect FS with low power consumption and high spectral purity