Fast extraction of defect size distribution using a single layer short flow NEST structure

Author

Hess, Christopher ; Stashower, David ; Stine, Brian E. ; Weiland, Larg H. ; Verma, Gaurav ; Miyamoto, Koji ; Inoue, Kotaro

Author_Institution

PDF Solutions Inc., San Jose, CA, USA

Volume

14

Issue

4

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

330

Lastpage

337

Abstract

Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield

Keywords

inspection; integrated circuit testing; integrated circuit yield; chip yield; data analysis; defect density; defect inspection; defect size distribution; electrical measurement; fault detection; killer defect; nested serpentine lines; process control; process data extraction; semiconductor device; single layer short flow NEST structure; test structure; turn around time; Data analysis; Data mining; Electric variables measurement; Electrical fault detection; Inspection; Manufacturing; Process control; Semiconductor device measurement; Size measurement; Testing;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.964320

Filename

964320