Title :
Queueing network models in the design and analysis of semiconductor wafer fabs
Author :
Kumar, Sunil ; Kumar, P.R.
Author_Institution :
Graduate Sch. of Bus., Stanford Univ., CA, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
We provide an introduction to the application of queueing network models to the design and analysis of semiconductor wafer fabs. We introduce the basic issues that confront the system manager and discuss a variety of queueing network based tools for addressing these issues. A representative collection of existing results in this area is also briefly surveyed
Keywords :
integrated circuit manufacture; production control; queueing theory; WIP; in-process material; performance evaluation; queueing network models; scheduling; semiconductor wafer fabs; work-in-process inventory; Intelligent networks; Job shop scheduling; Manufacturing systems; Performance analysis; Queueing analysis; Semiconductor device manufacture; Semiconductor device modeling; Stability; Telephony; Virtual manufacturing;
Journal_Title :
Robotics and Automation, IEEE Transactions on
