DocumentCode
1549329
Title
A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array
Author
Hsiao, Shen-Fu ; Shiue, Wei-Ren
Author_Institution
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume
11
Issue
11
fYear
2001
fDate
11/1/2001 12:00:00 AM
Firstpage
1149
Lastpage
1159
Abstract
A new recursive algorithm with hardware complexity of O(log2 N) is derived for fast computation of N×N 2-D discrete cosine transforms (2-D DCTs). It first converts the original 2-D data matrices into 1-D vectors and then employs different partition methods for the input and output indices in the 1-D vector space. Afterward, the algorithm computes the corresponding 2-D complex DCT (2-D CCT) and then uses a post-addition step to produce simultaneously two 2-D DCT outputs. The decomposed form of the 2-D recursive algorithm looks like a radix-4 fast Fourier transform algorithm. The common entries in each row of the butterfly-like matrix are factored out in order to reduce the number of multipliers needed during implementation. A new linear architecture for the derived algorithm is presented which leads to a hardware-efficient architectural design requiring only log2N complex multipliers plus 3log2N complex adders/subtractors for the computation of a 2-D N×N CCT
Keywords
computational complexity; data compression; digital arithmetic; discrete cosine transforms; image coding; matrix algebra; recursive estimation; systolic arrays; transform coding; 1D vectors; 2D DCT; 2D complex DCT; 2D data matrices; 2D discrete cosine transforms; 2D recursive algorithm; butterfly-like matrix; complex adders/subtractors; complex multipliers; discrete cosine transforms; fast Fourier transform algorithm; hardware complexity; hardware-efficient algorithm; hardware-efficient architectural design; image coding; input indices; linear architecture; linear array; output indices; post-addition; recursive algorithm; systolic arrays; Arithmetic; Computer architecture; Costs; Discrete cosine transforms; Fast Fourier transforms; Hardware; Matrix converters; Matrix decomposition; Partitioning algorithms; Vectors;
fLanguage
English
Journal_Title
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher
ieee
ISSN
1051-8215
Type
jour
DOI
10.1109/76.964780
Filename
964780
Link To Document