Noise optimization of an inductively degenerated CMOS low noise amplifier

Author

Andreani, Pietro ; Sjöland, Henrik

Author_Institution

Dept. of Electroscience, Lund Univ., Sweden

Volume

48

Issue

9

fYear

2001

fDate

9/1/2001 12:00:00 AM

Firstpage

835

Lastpage

841

Abstract

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels

Keywords

CMOS analogue integrated circuits; circuit optimisation; equivalent circuits; integrated circuit design; integrated circuit noise; linear network analysis; linear network synthesis; low-power electronics; minimisation; radiofrequency amplifiers; CMOS low noise amplifier; capacitance insertion; gate induced current noise; inductive source degeneration topology; inductively degenerated LNA; low power consumption levels; noise optimization; noise performance; noise reduction; very low noise figures; CMOS technology; Capacitance; Circuit noise; Energy consumption; Low-noise amplifiers; Noise figure; Noise reduction; Receivers; Thermal resistance; Topology;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.964996

Filename

964996