• DocumentCode
    1549762
  • Title

    Fault-secure parity prediction Booth multipliers

  • Author

    Nicolaidis, Michael ; Duarte, Ricardo O.

  • Author_Institution
    Reliable Integrated Syst. Group, TIMA Lab., Grenoble, France
  • Volume
    16
  • Issue
    3
  • fYear
    1999
  • fDate
    6/21/1905 12:00:00 AM
  • Firstpage
    90
  • Lastpage
    101
  • Abstract
    Parity prediction arithmetic operators are compatible with data paths and memory systems checked by parity codes. The authors extend their theory for achieving fault-secure design of parity prediction multipliers and dividers to Booth multipliers using operand recoding
  • Keywords
    digital arithmetic; fault tolerant computing; multiplying circuits; Booth multipliers; arithmetic operators; fault-secure design; operand recoding; parity prediction; Circuit topology; Complexity theory; Decoding; Digital arithmetic; Equations; Hardware; Routing; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.785842
  • Filename
    785842
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1549762