A parallel flash translation layer based on page group-block hybrid-mapping method

NAND flash memory has been widely used in consumer electronic devices. However, the write and erase operations consume too much time, creating a bottleneck in system performance, which is its main drawback. Thus, improving flash memory performance is critical in enhancing user experience of consumer electronic devices. Parallel flash memory was developed to support parallel operations of flash memories. However, no currently used flash translation layers (FTLs) can fully support this ideal feature of the flash memory. An efficient and simple parallel FTL (PFTL) is presented in the present paper to maximize the I/O parallelizability of flash memories. PFTL not only addresses the requests from the upper layer file system in parallel but also reclaims the invalid blocks in parallel. A trace-driven simulation using flash storage system simulator was conducted to evaluate PFTL. The experimental results show that the time used for the read and write operations was decreased by approximately 30% under both real-world and benchmark workloads. In addition, PFTL cut the erase time by around 50%. Thus, the I/O performance of consumer electronic devices can be largely improved by using PFTL.