Low-power circuit implementation for partial-product addition using pass-transistor logic

A low-power circuit implementation that performs partial-product addition within a 16×16-bit parallel multiplier is presented. The circuits are based on 0.8 μm and 0.35 μm BiCMOS processes and utilise mainly pass-transistor logic circuits. Unlike other pass-transistor implementations reported, the proposed circuits fully exploit the non-full-swing nature of the pass-transistor circuits, thus achieving low power operation. Despite the poorer current drive capability of the non-full-swing nodes, speed performance is maintained by stacking as few pass transistors in series as possible, and keeping the capacitive loading of the non-full-swing nodes as low as possible. The proposed implementation consists of a low-power 32-bit carry-select (CS) two-operand adder and a Wallace tree adder utilising a non-full-swing pass-transistor 4-2 compressor. Significant improvement in terms of power has been achieved when compared with existing circuits, thus making the proposed implementation suitable for a low-power high performance multipliers