Alternative facility layouts for semiconductor wafer fabrication facilities

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on fab cycle time of a number of alternative layouts or machine dedication policies using a process for manufacturing three-dimensional (3-D) complementary metal-oxide-semiconductor (CMOS) devices as a research vehicle. We examine the performance of the layouts under different levels of machine breakdown, utilization, transfer time between stations, and setup times. Results show that cellular layouts, where machines are dedicated to a limited number of process steps, require more machinery but perform well when setup and transfer times are high and machinery is reliable. As machines become more unreliable, the flexibility of the process layouts becomes a major advantage. An interesting result is that the addition of modest amounts of extra capacity at critical workstations can significantly improve the cycle time performance of a fab