Intentional overstress trimming of active semiconductor devices

Author

Hughes, David W. ; Feeney, Robert K.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

Volume

37

Issue

11

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

2282

Lastpage

2284

Abstract

An alternative methodology for adjusting the performance of electronic systems to ensure that they are operating according to the required specifications is described. Intentional electrical overstress is employed to systematically adjust the performance of integrated devices and circuits. It is shown that such an approach can trim selected circuits even after they have been assembled into packages. The trimming approach discussed is based upon the introduction of systematic and repeatable changes in transistor parameters by energetic pulses applied between appropriate terminals of the device. A preliminary reliability assessment of the technique has been performed, and the available results are discussed

Keywords

bipolar integrated circuits; field effect integrated circuits; integrated circuit technology; life testing; reliability; active semiconductor devices; energetic pulses; integrated devices; intentional electrical overstress; overstress trimming; reliability assessment; repeatable changes in transistor parameters; systematically adjust; trim after packaging; trim selected circuits; trimming approach; Assembly; Bipolar transistors; Electronics packaging; Integrated circuit reliability; Manufacturing processes; Metallization; Pulse amplifiers; Resistors; Semiconductor device packaging; Semiconductor devices;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.62289

Filename

62289