Title :
Communication-Aware Globally-Coordinated On-Chip Networks
Author :
Jin, Yuho ; Kim, Eun Jung ; Pinkston, Timothy Mark
Author_Institution :
Dept. of Electr. Eengineering-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
With continued Moore´s law scaling, multicore-based architectures are becoming the de facto design paradigm for achieving low-cost and performance/power-efficient processing systems through effective exploitation of available parallelism in software and hardware. A crucial subsystem within multicores is the on-chip interconnection network that orchestrates high-bandwidth, low-latency, and low-power communication of data. Much previous work has focused on improving the design of on-chip networks but without more fully taking into consideration the on-chip communication behavior of application workloads that can be exploited by the network design. A significant portion of this paper analyzes and models on-chip network traffic characteristics of representative application workloads. Leveraged by this, the notion of globally coordinated on-chip networks is proposed in which application communication behavior-captured by traffic profiling-is utilized in the design and configuration of on-chip networks so as to support prevailing traffic flows well, in a globally coordinated manner. This is applied to the design of a hybrid network consisting of a mesh augmented with configurable multidrop (bus-like) spanning channels that serve as express paths for traffic flows benefiting from them, according to the characterized traffic profile. Evaluations reveal that network latency and energy consumption for a 64-core system running OpenMP benchmarks can be improved on average by 15 and 27 percent, respectively, with globally coordinated on-chip networks.
Keywords :
multiprocessing systems; network-on-chip; Moore law; OpenMP benchmarks; communication-aware globally-coordinated on-chip networks; configurable multidrop spanning channels; multicore-based architectures; on-chip interconnection network; on-chip network traffic; traffic profiling; Bandwidth; Correlation; Hardware; Multicore processing; Program processors; System-on-a-chip; On-chip network design; application communication characterization; performance modeling.;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
DOI :
10.1109/TPDS.2011.164