• DocumentCode
    1551277
  • Title

    Efficient test cost reduction procedure for parallel-serial scan circuits

  • Author

    Solana, J.M.

  • Author_Institution
    Dept. de Electron. y Comput., Cantabria Univ., Santander, Spain
  • Volume
    37
  • Issue
    21
  • fYear
    2001
  • fDate
    10/11/2001 12:00:00 AM
  • Firstpage
    1277
  • Lastpage
    1278
  • Abstract
    An efficient test generation procedure aimed at reducing test application cost in parallel-serial scan (PASE-scan) circuits is presented. The procedure is based on the structure and configuration of this type of full-scan circuits. The results obtained with a set of ISCAS89 benchmark circuits are provided, showing the effectiveness of this technique as regards test clock reduction
  • Keywords
    integrated circuit testing; VLSI; full-scan design; parallel-serial scan circuit; test pattern generation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20010868
  • Filename
    968430
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1551277