Title :
Redistribution of Electrical Interconnections for Three-Dimensional Wafer-Level Packaging With Silicon Bumps
Author :
Wu, Guoqiang ; Xu, Dehui ; Xiong, Bin ; Wang, Yuelin
Author_Institution :
State Key Lab. of Transducer Technol., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China
Abstract :
In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D wafer-level packaging. A cap wafer with silicon bumps and electrical feedthroughs is bonded together with a device wafer using wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the cap wafer and the metal pads on the device wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the cap wafer and the device wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.
Keywords :
aluminium alloys; electrical contacts; elemental semiconductors; eutectic structure; gold alloys; integrated circuit interconnections; micromechanical resonators; silicon; wafer bonding; wafer level packaging; 3D wafer-level packaging; AuAl-Si; bonding materials; bonding process; cap wafer; device wafer; electrical feedthroughs; electrical interconnections redistribution; gold-aluminum eutectic; hermetic packaging; high performance MEMS resonator; mechanical bond; metal pads; potential application; silicon bumps; three-dimensional wafer-level packaging; wafer-level glass-frit bonding technology; wafer-level hermetic sealing; Bonding; Glass; Micromechanical devices; Optical resonators; Packaging; Silicon; Wafer scale integration; 3-D packaging; Redistribution of electrical interconnection; silicon bumps; wafer-level packaging;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2200231