Realizations of parallel and multibit-parallel shift register generators

We consider how to realize parallel shift register generators (PSRG) and multibit PSRGs, which can be directly used for parallel frame synchronous scrambling (FSS) in the bit- and multibit-interleaved multiplexing environments. We first describe the structure of PSRGs in terms of three parameters-the state transition matrix, the initial state vector, and the generating vectors. Then we discuss how to determine the three parameters of PSRGs that generate the desired parallel sequences in general. We further develop a method for the realization of minimum length PSRGs, and for the realization of PSRGs with minimized circuit complexity. Finally, we consider how to realize minimal PSRGs for use in multibit-parallel scrambling. The results are summarized in four sets of theorems, and are demonstrated through four examples