DocumentCode :
1552058
Title :
Design and evaluation of a high throughput robust router for network-on-chip
Author :
Alhussien, A. ; Wang, Chingyue ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Univ. of California-Irvine, Irvine, CA, USA
Volume :
6
Issue :
3
fYear :
2012
fDate :
5/1/2012 12:00:00 AM
Firstpage :
173
Lastpage :
179
Abstract :
Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.
Keywords :
fault tolerance; network-on-chip; telecommunication network routing; NoC systems; adaptive routing algorithm; deadlock freedom; deep submicron technology; fault tolerant router design; high throughput robust router; high-performance computing; manufacture defects; multiple processors; network links; network-on-chip systems; router components; running-time vulnerability; virtual channels;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt.2011.0082
Filename :
6230789
Link To Document :
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