Delay time sensitivity analysis of multi-generation BiCMOS digital circuits

The speed sensitivity of BiCMOS circuits to changes in the key MOS/BJT device parameters is analysed. The study takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel length and width, threshold voltage, and oxide thickness of the MOS transistor. The relationships between the key process parameters and the overall speed sensitivity are reported. The analysis also covers the effects of the output load capacitance, scaling the technology, and the quality of the bipolar device on the delay sensitivity. Sensitivity coefficients are defined and generated conventional BiCMOS circuit as well as two recently reported circuits designed for low-voltage operation. A method to calculate the worst case speed degradation for a given set of device and process parameters´ tolerances is described. HSPICE is used to generate the numerical results for the three technologies (5 V, 0.8 μm), (3.3 V, 0.5 μm), and (2.2 V, 0.2 μm)