High-speed dual-modulus prescaler architecture for programmable digital frequency dividers

A new high-speed architecture for a dual-modulus prescaler N/N+1 divider is presented and compared to the widely used Johnson counter, in addition to some other approaches that have inherent limitations of speed when the ´+1´ of the N+1 divider is processed. This high-speed structure allows a speed similar to that of a simple divider-by-two from which it derives