Title :
Strategies for low-cost test
Author :
Kapur, Rohit ; Chandramouli, R. ; Williams, T.W.
Abstract :
More collaboration between EDA, semiconductor, and ATE industry segments can improve the manufacturing test environment. The authors discuss how these improvements can dramatically reduce the cost of test and lead to a new generation of DFT-aware ATE and ATE-aware DFT
Keywords :
automatic test equipment; automatic test pattern generation; costing; design for testability; economics; integrated circuit testing; production testing; ATE-aware DFT; ATPG; DFT-aware ATE; EDA; capital cost; design methodologies; low-cost test strategies; manufacturing test environment; test costs; test methodologies; Automatic testing; Built-in self-test; Costs; Crosstalk; Delay; Design for testability; Logic arrays; Manufacturing; Semiconductor device testing; System testing;
Journal_Title :
Design & Test of Computers, IEEE
