• DocumentCode
    1553072
  • Title

    Strategies for low-cost test

  • Author

    Kapur, Rohit ; Chandramouli, R. ; Williams, T.W.

  • Volume
    18
  • Issue
    6
  • fYear
    2001
  • Firstpage
    47
  • Lastpage
    54
  • Abstract
    More collaboration between EDA, semiconductor, and ATE industry segments can improve the manufacturing test environment. The authors discuss how these improvements can dramatically reduce the cost of test and lead to a new generation of DFT-aware ATE and ATE-aware DFT
  • Keywords
    automatic test equipment; automatic test pattern generation; costing; design for testability; economics; integrated circuit testing; production testing; ATE-aware DFT; ATPG; DFT-aware ATE; EDA; capital cost; design methodologies; low-cost test strategies; manufacturing test environment; test costs; test methodologies; Automatic testing; Built-in self-test; Costs; Crosstalk; Delay; Design for testability; Logic arrays; Manufacturing; Semiconductor device testing; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.970423
  • Filename
    970423
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1553072