DocumentCode
1553451
Title
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
Author
Chang, Ray-I ; Hsiao, Pei-Yung
Author_Institution
Inst. of Inf. Sci., Acad. Sinica, Taipei, Taiwan
Volume
8
Issue
5
fYear
1997
fDate
9/1/1997 12:00:00 AM
Firstpage
1049
Lastpage
1064
Abstract
In this paper, a three-layer force-directed self-organizing map is designed to resolve the circuit placement problem with arbitrarily shaped rectilinear modules. The proposed neural model with an additional hidden layer can easily model a rectilinear module by a set of hidden neurons to correspond the partitioned rectangles. With the collective computing from hidden neurons, these rectilinear modules can correctly interact with each other and finally converge to a good placement result. In this paper, multiple contradictory criteria are accounted simultaneously during the placement process, in which, both the wire length and the module overlap are reduced. The proposed model has been successfully exploited to solve the time consuming rectilinear module placement problem. The placement results of real rectilinear test examples are presented, which demonstrate that the proposed method is better than the simulated annealing approach in the total wire length. The appropriate parameter values which yield good solutions are also investigated
Keywords
VLSI; circuit layout CAD; integrated circuit layout; optimisation; self-organising feature maps; VLSI circuit placement; force-directed self-organizing maps; molecular model; multiple contradictory criteria; neural model; optimisation; query based learning; rectilinear modules; Central Processing Unit; Circuit simulation; Information science; Neural networks; Neurons; Parallel processing; Self organizing feature maps; Simulated annealing; Very large scale integration; Wire;
fLanguage
English
Journal_Title
Neural Networks, IEEE Transactions on
Publisher
ieee
ISSN
1045-9227
Type
jour
DOI
10.1109/72.623207
Filename
623207
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