Title :
A highly reliable low temperature Al-Cu line/via metallization for sub-half micrometer CMOS
Author :
Joshi, R.V. ; Dalal, H. ; Filippi, R.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
We present significant advances over the current art in terms of enhanced electromigration lifetime, low temperature deposition, and improved damascene capability of Al-Cu via/line structure. The electromigration data shows that Al-Cu via/interconnect structure deposited by a new low pressure sputtering process (LPS) results in at least "9×" better electromigration lifetime (t/sub 50/) to that of conventionally used CVD W stud/Al-Cu interconnect structure. This significant improvement in the reliability may be attributed to the "breakthrough" in void-free filling of high aspect ratio (3 to 4) sub-half micrometer vias with low resistivity metal such as Al-Cu at as low temperature as room temperature. The LPS process eliminates the need of a collimator normally used to fill or coat the vias and improves throughput by a factor of 5× at least compared to collimation. The extendibility of this technique beyond 0.25 μm contact geometries is demonstrated. The integration of the LPS process, Al-Cu via/interconnects using damascene process demonstrates a working 512 K SRAM chip with 0.5 μm minimum groundrules.
Keywords :
integrated circuit metallisation; 0.25 mum; 0.5 mum; 3.6 ns; 512 kbit; Al-Cu line/via metallization; AlCu; SEM; SRAM chip; access time; damascene capability; electromigration lifetime; high aspect ratio via filling; low pressure sputtering process; low resistivity metal; low temperature deposition; minimum groundrules; reliability; room temperature; step coverage; sub-half micrometer CMOS; throughput; void-free filling; Art; Collimators; Conductivity; Electromigration; Filling; Geometry; Metallization; Sputtering; Temperature; Throughput;
Journal_Title :
Electron Device Letters, IEEE