DocumentCode
1554358
Title
New traffic model for performance analysis of processor-memory multistage interconnection networks
Author
Edirisooriya, S. ; Edirisooriya, G.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Volume
27
Issue
20
fYear
1991
Firstpage
1813
Lastpage
1816
Abstract
Multistage interconnection networks (MINs) provide cost effective, high bandwidth processor-memory communication in multiprocessor systems. The authors propose a nonuniform traffic model to analyse performance of processor-memory MINs, in the presence of switch and link failures.
Keywords
computer architecture; digital communication systems; fault tolerant computing; multiprocessor interconnection networks; switching theory; link failures; multiprocessor systems; multistage interconnection networks; nonuniform traffic model; performance analysis; switch failures; traffic model; wideband processor-memory communication;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19911127
Filename
97193
Link To Document