Title :
A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
Author :
Yang, Wenhua ; Kelly, Dan ; Mehr, Iuri ; Sayuk, Mark T. ; Singer, Larry
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
fDate :
12/1/2001 12:00:00 AM
Abstract :
This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm2 ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V
Keywords :
CMOS integrated circuits; analogue-digital conversion; bootstrap circuits; integrated circuit noise; low-power electronics; pipeline processing; sample and hold circuits; 0.35 micron; 14 bit; 3 V; 340 mW; Nyquist input; buffered bootstrapping; capacitor matching; charge injection; common-mode compliance; differential nonlinearity; double-poly triple-metal CMOS process; integral nonlinearity; pipeline analog-to-digital converter; power consumption; signal-to-noise ratio; spurious-free dynamic range; track-and-hold amplifier; Calibration; Capacitors; Circuits; Dynamic range; Energy consumption; Linearity; Pipelines; Sampling methods; Signal resolution; Signal to noise ratio;
Journal_Title :
Solid-State Circuits, IEEE Journal of
