A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

Author

Tadjpour, Shahrzad ; Cijvat, Ellie ; Hegazi, Emad ; Abidi, Asad A.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

36

Issue

12

fYear

2001

fDate

12/1/2001 12:00:00 AM

Firstpage

1992

Lastpage

2002

Abstract

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; cellular radio; flicker noise; integrated circuit noise; phase noise; radio receivers; 0.35 micron; 2.5 V; 22 mA; 5 dB; 8 mA; 900 MHz; CMOS; LO frequencies; analog channel selection; blocking signals; dual conversion; dual-conversion low-IF GSM receiver; flicker noise; image rejection; on-chip resonator; phase-noise specifications; Bit error rate; Circuits; Frequency synthesizers; GSM; Image converters; Low pass filters; Noise figure; Noise measurement; Radio frequency; Transceivers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.972150

Filename

972150