• DocumentCode
    1555279
  • Title

    A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

  • Author

    Chiang, Te-Kuang

  • Author_Institution
    Department of Electrical Engineering, National University of Kaohsiung, Advanced Devices Simulation Laboratory, Kaohsiung, Taiwan
  • Volume
    59
  • Issue
    9
  • fYear
    2012
  • Firstpage
    2284
  • Lastpage
    2289
  • Abstract
    Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.
  • Keywords
    Computational modeling; Logic gates; MOSFETs; Mathematical model; Semiconductor device modeling; Threshold voltage; Bulk conduction mode; junctionless (JL) double-gate MOSFETs; quasi-2-D scaling theory; threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2012.2202119
  • Filename
    6236119