DocumentCode
1555591
Title
Improved hot-electron reliability in high-performance, multilevel-metal CMOS using deuterated barrier-nitride processing
Author
Clark, W.F. ; Ference, T.G. ; Mittl, S.W. ; Burnham, J.S. ; Adams, E.D.
Author_Institution
IBM Microelectron. Div., Essex Junction, VT, USA
Volume
20
Issue
10
fYear
1999
Firstpage
501
Lastpage
503
Abstract
Deuterated barrier-nitride films and anneals in a deuterium ambient prior to first-metal have been incorporated into a conventional high-performance CMOS process and subjected to subsequent processing through five levels of metal. Device hot-electron stress results confirm that, even though some initial relaxation of the transistor lifetime improvement is observed with further hot processing, significant lifetime improvement can be achieved through full wafer processing through five levels of metal. The barrier-nitride acts as a reservoir for deuterium, maintaining high concentrations in the device regions through further processing. These results support the efficacy of using a deuterium reservoir to achieve a hot-electron hardened transistor.
Keywords
CMOS integrated circuits; MOSFET; annealing; deuterium; hot carriers; hydrogenation; integrated circuit metallisation; integrated circuit reliability; ion-surface impact; secondary ion mass spectra; semiconductor device metallisation; semiconductor device reliability; 0.25 mum; 2.5 V; CMOSFET; D/sub 2/ reservoir; ND/sub 3/; SIMS; SiD/sub 4/; anneals; deuterated barrier-nitride processing; full wafer processing; high-performance CMOS process; hot-electron hardened transistor; hot-electron reliability; hot-electron stress; hydrogen forward scattering; multilevel-metal CMOS; transistor lifetime improvement; Annealing; CMOS process; Degradation; Deuterium; Hot carriers; Hydrogen; MOSFETs; Neodymium; Reservoirs; Silicon;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.791923
Filename
791923
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