DocumentCode :
1555633
Title :
Suppression of boron penetration for p/sup +/ stacked poly-Si gates by using inductively coupled N2 plasma treatment
Author :
Cheng, Huang-Chung ; Lai, Wen-Koi ; Hwang, Chuan-Chou ; Juang, Miin-Horng ; Chu, Shu-Ching ; Liu, Tzeng-Feng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
20
Issue :
10
fYear :
1999
Firstpage :
535
Lastpage :
537
Abstract :
Nitridation of stacked poly-Si gates by inductively coupled N/sub 2/ plasma (ICNP) treatment has been shown to suppress boron penetration and improve gate oxide integrity. The ICNP treatments on the stacked poly-Si layers create nitrogen-rich layers not only between the stacked poly-Si layers but also in the gate oxide after post implant anneal, thus resulting in effective retardation of boron diffusion. In addition, positioning of ICNP treatment closer to gate oxides leads to higher nitrogen peaks in the gate oxide region, resulting in further suppression of boron penetration and improvement of gate oxide reliability.
Keywords :
MOS capacitors; annealing; diffusion; elemental semiconductors; nitridation; plasma materials processing; secondary ion mass spectra; semiconductor device breakdown; semiconductor device reliability; silicon; B penetration suppression; MOS capacitors; N-rich layers; N/sub 2/; N/sub 2/ ICP treatment; SIMS profiles; Si; Si-SiO/sub 2/; Weibull plot; charge to breakdown; furnace annealing; gate oxide integrity; gate oxide reliability; inductively coupled N/sub 2/ plasma treatment; nitridation; p/sup +/ stacked polysilicon gates; post implant anneal; Annealing; Boron; CMOS technology; Implants; Lead compounds; MOSFET circuits; Materials science and technology; Nitrogen; Plasmas; Threshold voltage;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.791934
Filename :
791934
Link To Document :
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