An ITLDD CMOS process with self-aligned reverse-sequence LDD/channel implantation

Author

Pfiester, James R. ; Sivan, Richard D. ; Gunderson, Craig D. ; Crain, Neil E. ; Lin, Jung-Hui ; Liaw, Hang M. ; Seelbach, Chris A. ; Baker, Frank K.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

38

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

2460

Lastpage

2464

Abstract

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET´s with improved short-channel behavior due to the smaller lateral source/drain diffusion

Keywords

CMOS integrated circuits; hot carriers; integrated circuit technology; ion implantation; photolithography; ITLDD CMOS process; hot-carrier protection; inverse-T LDD CMOS process; lateral source/drain diffusion; nitride sidewall spacers; optical lithography; selective polysilicon deposition; self-aligned reverse-sequence LDD/channel implantation; sub-half-micrometer gate length MOSFETs; thick polysilicon gate regions; thin polysilicon gate regions; Annealing; CMOS process; Etching; Hydrogen; Implants; Length measurement; Lithography; MOS devices; Nitrogen; Silicon;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.97409

Filename

97409