Title :
A 0.5-μm very-high-speed silicon bipolar devices technology U-groove-isolated SICOS
Author :
Shiba, Takeo ; Tamaki, Yoichi ; Kure, Tokuo ; Kobayashi, Takashi ; Nakaminra, T.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
A 0.5-μm high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5-μm SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at Fin =1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; 0.5 micron; 27 ps; ECL gate delay; U-groove isolation; base resistance; double polysilicon planarization; emitter-coupled-logic; large-grain base polysilicon; self-alignment technology; shallow impurity profile; sidewall base contact structure; substrate capacitance; very high speed bipolar technology; Analytical models; Circuit simulation; Cutoff frequency; Delay effects; Impurities; Isolation technology; Parasitic capacitance; Performance analysis; Planarization; Silicon;
Journal_Title :
Electron Devices, IEEE Transactions on
