A high-resolution time interpolator based on a delay locked loop and an RC delay line

Author

Mota, Manuel ; Christiansen, Jorgen

Author_Institution

CERN, Geneva, Switzerland

Volume

34

Issue

10

fYear

1999

fDate

10/1/1999 12:00:00 AM

Firstpage

1360

Lastpage

1366

Abstract

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7-μm CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology

Keywords

CMOS integrated circuits; calibration; delay lines; delay lock loops; interpolation; 0.7 micron; 160 MHz; RC delay line; autocalibration circuit; code density tests; delay locked loop; digital CMOS technology; reference clock; resolution; rms error; self calibrating DLL; start-up calibration; time interpolator; CMOS technology; Calibration; Circuit testing; Clocks; Delay effects; Delay lines; Interpolation; Performance evaluation; Radio control; Temperature dependence;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.792603

Filename

792603