A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

Author

Law, C.F. ; Rofail, S.S. ; Yeo, K.S.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

Volume

34

Issue

10

fYear

1999

fDate

10/1/1999 12:00:00 AM

Firstpage

1395

Lastpage

1399

Abstract

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz

Keywords

BiCMOS logic circuits; VLSI; integrated circuit design; low-power electronics; multiplying circuits; 0.8 micron; 10 MHz; 10.4 ns; 16 bit; 3.3 V; 38 mW; average power dissipation; double-metal double-poly BiCMOS process; low-power electronics; nonfull-swing nature; parallel multiplier; partial product generator; partial-product addition circuitry; pass-transistor logic circuits; speed performance; supply voltage; very large scale integration; worst case multiplication time; BiCMOS integrated circuits; CMOS logic circuits; Circuit simulation; Circuit testing; Logic circuits; Logic design; Logic devices; Power dissipation; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.792613

Filename

792613