Title :
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips
Author :
Papa, David ; Alpert, Charles ; Sze, Cliff ; Li, Zhuo ; Viswanathan, Natarajan ; Nam, Gi-Joon ; Markov, Igor L.
Abstract :
In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.
Keywords :
clocks; flip-flops; network synthesis; system-on-chip; CPU designs; clock-network optimization; flip-flops; latches; next-generation electronic-design-automation methodology; physical synthesis; system-on-chip; Clocks; Cloning; Degradation; Latches; Logic gates; Optimization; Timing; physical synthesis; systems on chips;
Journal_Title :
Micro, IEEE
