Title :
An FPGA prototype of a forward error correction (FEC) decoder for ATSC digital TV
Author :
Yang, Haiyun ; Zhong, Yan ; Yang, Lin
Author_Institution :
Wireless Design Center, Cadence Design Syst. Inc., San Jose, CA, USA
fDate :
5/1/1999 12:00:00 AM
Abstract :
The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively
Keywords :
Reed-Solomon codes; VLSI; comb filters; decoding; digital television; field programmable gate arrays; forward error correction; video codecs; ATSC digital TV; FEC decoder; FEC encoder/decoder system; FPGA board; FPGA prototype; NTSC rejection filter; RS decoder; Reed-Solomon decoder; VLSI architecture; architecture design; comb filter; de-interleaver; de-randomizer; forward error correction decoder; performance; testing vectors; threshold of visibility; trellis decoder; Bit error rate; Decoding; Demodulation; Digital TV; Field programmable gate arrays; Filters; Forward error correction; Notice of Violation; Prototypes; System testing;
Journal_Title :
Consumer Electronics, IEEE Transactions on
