DocumentCode :
1556873
Title :
Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results
Author :
Lorenz, Jürgen K. ; Bär, Eberhard ; Clees, Tanja ; Evanschitzky, Peter ; Jancke, Roland ; Kampen, Christian ; Paschen, Uwe ; Salzig, Christian P J ; Selberherr, Siegfried
Author_Institution :
Fraunhofer Inst. for Integrated Syst. & Device Technol. (IISB), Erlangen, Germany
Volume :
58
Issue :
8
fYear :
2011
Firstpage :
2227
Lastpage :
2234
Abstract :
Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. Five Fraunhofer institutes joined forces to address these issues. Their own software tools, e.g., for lithography/topography simulation, mixed-mode device simulation, compact model extraction, and behavioral modeling, have been combined with commercial tools to establish a hierarchical system of simulators in order to analyze process variations from their source, e.g., in a lithography step, through device fabrication up to the circuit and system levels.
Keywords :
digital simulation; electronic engineering computing; integrated circuit modelling; technology CAD (electronics); Fraunhofer institutes; TCAD; behavioral modeling; device architecture; hierarchical simulation; integrated circuits; mixed-mode device simulation; model extraction; process variations; software tools; technology computer-aided design; topography simulation; Integrated circuit modeling; Lithography; Logic gates; Random access memory; Semiconductor device modeling; Threshold voltage; Transistors; Circuit simulation; manufacturability; process modeling; semiconductor device modeling; sensitivity; yield;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2011.2150226
Filename :
5887403
Link To Document :
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