Title :
A cost-efficient and fully-pipelinable architecture for DCT/IDCT
Author :
Hsiao, Shen-Fu ; Shiue, Wei-Ren ; Tseng, Jian-Ming
Author_Institution :
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fDate :
8/1/1999 12:00:00 AM
Abstract :
A novel low-cost and low-power linear array for computation of discrete cosine transform (DCT) and its inverse is derived from the heterogeneous dependence graphs representing the factorized coefficient matrices. Due to the novel algorithm and the corresponding efficient architectural design, the new DCT/IDCT processor is easily pipelined and the power consumption can be reduced significantly by turning off the operation of arithmetic units whenever possible
Keywords :
data compression; digital signal processing chips; discrete cosine transforms; graph theory; image coding; integrated circuit layout; inverse problems; matrix decomposition; parallel architectures; pipeline processing; DCT; IDCT; arithmetic units operation; cost-efficient fully-pipelinable architecture; discrete cosine transform; efficient architectural design; factorized coefficient matrices; heterogeneous dependence graphs; iscrete cosine transform; linear array; power consumption; Algorithm design and analysis; Arithmetic; Computer architecture; Costs; Discrete cosine transforms; Energy consumption; Hardware; Image coding; Matrix decomposition; Read only memory;
Journal_Title :
Consumer Electronics, IEEE Transactions on
