• DocumentCode
    1557172
  • Title

    Suppression of boron penetration in p-channel MOSFETs using polycrystalline Si/sub 1-x-y/GexCy gate layers

  • Author

    Stewart, E.J. ; Carroll, M.S. ; Sturm, James C.

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., NJ, USA
  • Volume
    22
  • Issue
    12
  • fYear
    2001
  • Firstpage
    574
  • Lastpage
    576
  • Abstract
    Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si/sub 1-x-y/Ge/sub x/C/sub y/ gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si/sub 1-x/Ge gate layers. Boron accumulates in the poly Si/sub 1-x-y/Ge/sub x/C/sub y/ layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si/sub 1-x-y/Ge/sub x/C/sub y/ appears to be electrically active, providing similar device performance compared to the poly Si or poly Si/sub 1-x/Ge/sub x/ gated devices.
  • Keywords
    Ge-Si alloys; MOSFET; annealing; carrier mobility; secondary ion mass spectra; segregation; semiconductor device measurement; semiconductor materials; Si/sub 1-x-y/Ge/sub x/C/sub y/; boron penetration suppression; charge carrier mobility; electrically active material; gate-oxide interface; p-channel MOSFETs; polycrystalline Si/sub 1-x-y/Ge/sub x/C/sub y/ gate layers; positive threshold voltage shifts; thin gate oxides; threshold voltage stability; Annealing; Boron alloys; Capacitors; Charge carrier mobility; Fabrication; MOSFETs; Silicon alloys; Stability; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.974581
  • Filename
    974581