Title :
Scan-Based Speed-Path Debug for a Microprocessor
Author :
Jing Zeng ; Mateja, M.A. ; Jing Wang ; Ruifeng Guo ; Wu-Tung Cheng
Author_Institution :
Apple, Capurtino, CA, USA
Abstract :
Identifying the actual speed limiting paths in silicon using traditional functional microprocessor tests can be very time-consuming and expensive because of limited observability of internal signals. This paper presents the development of a promising scan-based speed path diagnosis methodology and illustrates its application to a high performance microprocessor design.
Keywords :
integrated circuit design; microprocessor chips; Si; internal signals; microprocessor design; scan-based speed path diagnosis methodology; speed-path debug; Design optimization; Fault diagnosis; Microprocessors; Silicon; Timing analysis; at-speed test; diagnosis; silicon debug; speed-path debug; timing failure;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2012.2208353
